1. Field
This application relates generally to semiconductor devices and to methods of making the devices.
2. Background of the Technology
A field-effect transistor (FET) is a type of transistor commonly used for weak-signal amplification (e.g., for amplifying wireless signals). The device can amplify analog or digital signals. It can also switch DC or function as an oscillator. In an FET, current flows along a semiconductor path called the channel. At one end of the channel, there is an electrode called the source. At the other end of the channel, there is an electrode called the drain. The physical diameter of the channel is fixed, but its effective electrical diameter can be varied by the application of a voltage to a control electrode called the gate. The conductivity of the FET depends, at any given instant in time, on the electrical diameter of the channel. A small change in gate voltage can cause a large variation in the current from the source to the drain thereby allowing for amplification of signals.
A PiN diode is a diode with a wide, lightly doped ‘near’ intrinsic semiconductor region between p-type semiconductor and n-type semiconductor regions. A junction barrier Schottky (JBS) diode is also referred to as a merged PiN Schottky diode since it contains both PiN and Schottky barrier (i.e., metal-semiconductor) junctions.
Vertical Junction Field Effect Transistor (VJFET) and Static Induction Transistor (SIT) devices in SiC have been described in U.S. Pat. Nos. 5,903,020 and 6,767,783; and in U.S. Patent Application Publication No. 2007/0187715 A1. In the case of an SIT, a short channel length is typically preferred in order to keep the frequency response high. Therefore a shallow p+ gate implant that does not create sidewall implantation on the trenched source fingers is preferred. In the power VJFET structure, however, it is preferred to have a long channel length in order for the device to be able to prevent the electric field under high reverse bias from reducing the channel barrier and causing increased drain-source leakage currents or total breakdown. In U.S. Patent Application Publication No. 2007/0187715 A1, angled implantation on the source finger sidewalls is disclosed as a method to create a long gate doping profile along the source channel length. This method has several disadvantages, however. Namely, the wafer has to be rotated during implantation in order to prevent implant shadowing in the trenched structure. Additionally, the angled implant causes uniform implantation along the vertical axis of the structure from the channel into the source region causing two adjoining heavily doped regions (source and gate). The close nature of these two regions result in poor voltage handling capability. Additionally, angled implantation along this axis can create significant channeling of the ions resulting in a non-symmetrical gate-source junction, particularly for SiC substrates which are typically cut off-axis (e.g., at an angle of 2-8 degrees).
Accordingly, there still exists a need for improved methods of making semiconductor devices.